MEMORANDUM

TO: Mr. Gary Harding
FROM: Mandy Crozier
DATE: June 12, 1997
RE: Proposal to write Co-operative Education Student Guide: Working in a Simulation and Verification Environment.

The following is a proposal to develop a guide that will cover the job responsibilities of an Global Computing Corporation co-operative education student (co-op) in the GCC Microprocessor division, logic chip simulation and verification area. This proposal contains information on the contents of the proposed guide, the audience being targeted, my schedule to complete this assignment, and my qualifications to write this guide.

The guide will be classified as a technical background and instructional guide. I will write the initial draft and seek reviews and edit the initial final draft. It will be GCC's responsibility to print the final copy and ship it to prospective co-ops as the company deems appropriate. The rest of this proposal gives more detail on the specific outline and areas of the guide and a timetable on getting the guide finished.

Need for a Guide

Prior to starting work at GCC, I knew little about what my job responsibilities would be as a co-op other than what was mentioned during the interview with my recruiter. I remember thinking shortly after I accepted the offer to work at GCC, that it would have been useful to have been given some sort of guide, or handout detailing my job description. For first-term co-ops, this would certainly give them a better idea of what is expected of them on the job, and perhaps allay some doubts they might have about working in the development area of the computer industry.

Audience

 The guide will be written primarily with a prospective co-op in mind. The co-op will most likely be an Electrical Engineering major, with an interest in working in the hardware architecture development area upon graduation. Minimal technical knowledge about logic chip simulation and verification is required, although it is assumed that the co-op will have completed the first Electrical Circuits class, as well as the first Digital Design class, prior to starting work at GCC.

Description of the Guide

This guide should provide an Electrical Engineering student with sufficient background information to work in a simulation and verification area. It will contain diagrams and flow charts, as well as describe the technical background needed to verify a logic chip design.

Diagrams. The diagrams used in this guide will consist of flow charts, event trees, and event traces. The flow charts will methodically go through the process used to verify chip design. The event trees will graphically show the hierachy of the functions known to the automated test case generator. The event traces will display the results of a simulated output in a graphical environment, which allows the user to trace failures on a cycle-to-cycle basis.

Technical Background. The guide will discuss the technical background of generating, modifying and simulating test cases. It will give a description of the tools used by the simulation and verification team, as well as the background needed to operate these tools.

My Qualifications

I am a first semester Junior Electrical Engineering major from Texas A&M University. Prior to starting work at GCC, I completed these classes:

ELEN214 Electrical Circuits with Lab
ELEN248 Introduction to Digital Design
ELEN314 Linear Circuit Analysis

I found of particular use ELEN248 as it teaches the fundamental concepts needed to understand the work I do. While it was not a pre-requisite for this job, some prior programming knowledge in C/C++ is very useful.

As of June 1997, I have been assigned to the I/O Controller Development Department, working under the umbrella division of GCC Microprocessors: PowerPC Systems and Technology, for a period of 6 months. During this time, I have worked on a simulation and verification team for two chips. For the first four months of my co-op experience, I worked on a chip that was fairly close to completion. Most of my experience with that chip was in testing and verification, and this is what I will write about in this report. A month ago, I started on a new chip ground-up. On this project, my emphasis has been primarily in simulation design development. I have had the benefit of working on various aspects of chip simulation and verification from a co-op standpoint, and feel that I have the background and experience to write a report on what a prospective co-op can expect to do if assigned to a GCC Microprocessor area.

Plan for the Guide

I will deliver the report to your office on July 31, 1997. Here is my plan for completing this project:

1. Review past work through June 13
2. Conduct interviews finish June 20
3. Write preliminary draft finish June 27
4. Produce diagrams finish July 2
5. Finalize preliminary draft finish July 11
6. Deliver preliminary draft on July 18

Costs

There will be no costs involved in producing this guide, other than the costs of an hour a day for the next eight weeks to do the research, conduct the interviews and write the guide. I will deliver one hardcopy of the guide typed and bound, and the rest can be reproduced through softcopy on the network, as deemed appropriate by GCC.

Lists of Diagrams

 This is a tentative list of the diagrams I plan to incorporate in my guide:
  1. A program event tree built using the automated test program generator
  2. Flow chart of process used to verify a logic chip design
  3. An example of an AVP list
  4. An example of an All Event Trace (AET)

Tentative Outline

 
  I. Introduction
     A. Why co-op?
     B. Need for a co-op guide

 II. General Information
     A. First day on the job
     B. Learning curve

III. My Role
     A. Generating new test case
     B. Modifying existing test cases
     C. Simulating test cases

 IV. Conclusion
     A. Summarize the co-op experience
     B. The next step

Tentative Bibliography and References
  1. A. N. Rieck. Functional Specification. Document Version 0.1. GCC Corporation.

  2. R. E. Sepulveda. XVS AET Viewer. Document Version 1.0. GCC Corporation.

  3. K. L. Barrett, Simulation lead. Interview regarding automated test case generator documentation. June 13, 1997.

  4. A. J. Dingankar, Simulation team member. Interview regarding simulation environments. June 16-20, 1997.